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Cascaded Logic Gates in Nanophotonic Plasmon Networks
Hongxing Xu

Last modified: 2012-01-03


Modern electronics based on semiconductors is meeting the fundamental speed limit caused by the interconnect delay and large heat generation when the sizes of components reach nanometer scale. Photons as a carrier of the information are superior to electrons in bandwidth, density, speed, and dissipation. More over, photons could carry intensity, polarization, phase, and frequency information which could break through the limitation of binary system as in electronic devices. But due to the diffraction limitation, the photonic components and devices can not be fabricated small enough to be integrated densely. Surface plasmon polariton is quanta of collective oscillations of free electrons excited by photons in metal nanostrucrures, which offers a promising way to manipulate light at the nanoscale and to realize the miniaturization of photonic devices. Hence, plasmonic circuits and devices have been proposed for some time as a potential strategy for advancing semiconductor-based computing beyond the fundamental performance limitations of electronic devices, as epitomized by Moore's law.

A variety of individual plasmonic nanodevices have been intensively studied recently, but the crucial and necessary step to enable nanophotonic circuits for future information technology, namely cascade logics integrated on-chip, has not been achieved. Here we demonstrate that a nanophotonic binary logic NOR gate can be realized by cascading plasmonic OR and NOT gates in four-terminal nanowire networks. We explain the operating principle for the device based on quantum dot luminescence imaging, which reveal the interferences for different logic functions between propagating plasmon wave packets in the nanowire network in great detail. Since the NOR gate is logic complete, i.e. any Boolean logic gate can be constructed from it, our results could have a key role in defining a viable path for the development of novel subwavelength optical processor architectures.